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| ds123 (v2.9) may 09, 2006 www.xilinx.com 1 ? 2003-2006 xilinx, inc. all rights reserved. all xilinx tradem arks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . powerpc is a trademark of ibm, inc. all other trademarks are t he property of their respective owners. all specifications are su bject to change without notice. features ? in-system programmable proms for configuration of xilinx fpgas ? low-power advanced cmos nor flash process ? endurance of 20,000 program/erase cycles ? operation over full industrial temperature range (?40c to +85c) ? ieee standard 1149. 1/1532 boundar y-scan (jtag) support for programming, prototyping, and testing ? jtag command initiation of standard fpga configuration ? cascadable for storing longer or multiple bitstreams ? dedicated boundary-scan (jtag) i/o power supply (v ccj ) ? i/o pins compatible with voltage levels ranging from 1.5v to 3.3v ? design support using the xilinx alliance ise and foundation ise series software packages ? xcf01s/xcf02s/xcf04s ? 3.3v supply voltage ? serial fpga configuration interface (up to 33 mhz) ? available in small-footprint vo20 and vog20 packages. ? xcf08p/xcf16p/xcf32p ? 1.8v supply voltage ? serial or parallel fpga configuration interface (upto33mhz) ? available in small-footpr int vo48, vog48, fs48, and fsg48 packages ? design revision technology enables storing and accessing multiple design revisions for configuration ? built-in data decompressor compatible with xilinx advanced compression technology description xilinx introduces the platform flash series of in-system programmable configuration proms. available in 1 to 32 megabit (mbit) densities, these proms provide an easy-to-use, cost-effective, and reprogrammable method for storing large xilinx fpga configuration bi tstreams. the platform flash prom series includes both the 3.3v xcfxxs prom and the 1.8v xcfxxp prom. the xcfxxs version includes 4-mbit, 2-mbit, and 1-mbit proms that support master serial and slave serial fpga configuration modes ( figure 1, page 2 ). the xcfxxp version includes 32-mbit, 16-mbit, and 8-mbit proms that support master serial, slave serial, master selectmap, and slave selectmap fpga configuration modes ( figure 2, page 2 ). a summary of the platform flash prom family members and supported features is shown in ta bl e 1 . platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 2 r when the fpga is in master serial mode, it generates a configuration clock that drives the prom. with cf high, a short access time after ce and oe are enabled, data is available on the prom data (d0) pin that is connected to the fpga din pin. new data is available a short access time after each rising clock edge. the fpga generates the appropriate number of clock pulses to complete the configuration. when the fpga is in slave serial mode, the prom and the fpga are both clocked by an external clock source, or optionally, for the xcfxxp prom only, the prom can be used to drive the fpga?s configuration clock. the xcfxxp version of the platform flash prom also supports master selectm ap and slave selectmap (or slave parallel) fpga configuration modes. when the fpga is in master selectmap mode, the fpga generates a configuration clock that drives the prom. when the fpga is in slave selectmap mode, ei ther an external oscillator generates the configuration clock that drives the prom and the fpga, or optionally, the xcfxxp prom can be used to drive the fpga?s configuration clock. with busy low and cf high, after ce and oe are enabled, data is available on the proms data (d0-d7) pins. new data is available a short access time after each rising clock edge. the data is clocked into the fpga on the following rising edge of the cclk. a free-running oscillato r can be used in the slave parallel /slave selecmap mode. the xcfxxp version of the platform flash prom provides additional advanced features. a built-in data decompressor supports utilizing compressed prom files, and design revisioning allows multiple desi gn revisions to be stored on a single prom or stored across several proms. for design revisioning, external pins or internal control bits are used to select the active design revision. multiple platform flash prom devices can be cascaded to support the larger configuration files required when targeting larger fpga devices or targeting multiple fpgas daisy chained together. w hen utilizing th e advanced features for the xcfxxp platform flash prom, such as design revisioning, programming files which span cascaded prom devices can only be cr eated for cascaded chains containing only xcfxxp proms. if the advanced xcfxxp features are not enabled, then the cascaded chain can include both xcfxxp and xcfxxs proms. figure 1: xcfxxs platform flash prom block diagram control and jtag interface memory serial interface data (d0) serial mode data address clk ce tck tms tdi tdo oe/reset ceo data ds123_01_30603 cf fi figure 2: xcfxxp platform flash prom block diagram clkout ceo data (d0) (serial/parallel mode) d[1:7] (parallel mode) tck tms tdi tdo clk ce en_ext_sel oe/reset busy data data address rev_sel [1:0] cf control and jtag interface memory osc serial or parallel interface decompressor ds123_1 9 _122105 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 3 r the platform flash proms are compatible with all of the existing fpga device fa milies. a reference list of xilinx fpgas and the respective compatible platform flash proms is given in ta b l e 2 . a list of platform flash proms and their capacities is given in table 3, page 4 . ta bl e 2 : xilinx fpgas and compatible platform flash proms fpga configuration bitstream platform flash prom (1) virtex-5 lx xc5vlx30 8,374,016 xcf08p xc5vlx50 12,556,672 xcf16p xc5vlx85 21,845,632 xcf32p xc5vlx110 29,124,608 xcf32p xc5vlx220 53,139,456 xcf32p+xcf32p xc5vlx330 79,704,832 xcf32p+xcf32p+xcf16p virtex-4 lx xc4vlx15 4,765,568 xcf08p xc4vlx25 7,819,904 xcf08p xc4vlx40 12,259,712 xcf16p xc4vlx60 17,717,632 xcf32p xc4vlx80 23,291,008 xcf32p xc4vlx100 30,711,680 xcf32p xc4vlx160 40,347,008 xcf32p+xcf08p xc4vlx200 51,367,808 xcf32p+xcf32p virtex-4 fx xc4vfx12 4,765,568 xcf08p xc4vfx20 7,242,624 xcf08p xc4vfx40 14,936,192 xcf16p xc4vfx60 21,002,880 xcf32p xc4vfx100 33,065,408 xcf32p xc4vfx140 47,856,896 xcf32p+xcf16p virtex-4 sx xc4vsx25 9,147,648 xcf16p xc4vsx35 13,700,288 xcf16p xc4vsx55 22,749,184 xcf32p virtex-ii pro x xc2vpx20 8,214,560 xcf08p xc2vpx70 26,098,976 xcf32p virtex-ii pro xc2vp2 1,305,376 xcf02s xc2vp4 3,006,496 xcf04s xc2vp7 4,485,408 xcf08p xc2vp20 8,214,560 xcf08p xc2vp30 11,589,920 xcf16p xc2vp40 15,868,192 xcf16p xc2vp50 19,021,344 xcf32p xc2vp70 26,098,976 xcf32p xc2vp100 34,292,768 xcf32p (2) virtex-ii (3) xc2v40 360,096 xcf01s xc2v80 635,296 xcf01s xc2v250 1,697,184 xcf02s xc2v500 2,761,888 xcf04s xc2v1000 4,082,592 xcf04s xc2v1500 5,659,296 xcf08p xc2v2000 7,492,000 xcf08p xc2v3000 10,494,368 xcf16p xc2v4000 15,659,936 xcf16p xc2v6000 21,849,504 xcf32p xc2v8000 29,063,072 xcf32p virtex-e xcv50e 630,048 xcf01s xcv100e 863,840 xcf01s xcv200e 1,442,016 xcf02s xcv300e 1,875,648 xcf02s xcv400e 2,693,440 xcf04s xcv405e 3,430,400 xcf04s xcv600e 3,961,632 xcf04s xcv812e 6,519,648 xcf08p xcv1000e 6,587,520 xcf08p xcv1600e 8,308,992 xcf08p xcv2000e 10,159,648 xcf16p xcv2600e 12,922,336 xcf16p xcv3200e 16,283,712 xcf16p virtex xcv50 559,200 xcf01s xcv100 781,216 xcf01s xcv150 1,040,096 xcf01s xcv200 1,335,840 xcf02s xcv300 1,751,808 xcf02s xcv400 2,546,048 xcf04s xcv600 3,607,968 xcf04s xcv800 4,715,616 xcf08p xcv1000 6,127,744 xcf08p spartan-3e xc3s100e 581,344 xcf01s xc3s250e 1,352,192 xcf02s xc3s500e 2,267,136 xcf04s ta b l e 2 : xilinx fpgas and compatible platform flash proms (continued) fpga configuration bitstream platform flash prom (1) platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 4 r programming in-system programming in-system programmable proms can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin jtag protocol as shown in figure 3 . in-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. the programming data sequence is delivered to the device using either xilinx impact software and a xilinx download cable, a third-party jtag development system, a jtag-compatible board tester, or a simple microprocessor interface that emulates the jtag instruction sequence. the impact software also outputs serial vector format (svf) files for use with any tools that accept svf format, including automatic test equipment. during in-system programming, the ceo output is driven high. a ll other outputs are held in a high-impedance state or held at clamp levels during in-system programming. in-sys tem programming is fully supported across the recommended operating voltage and temperature ranges. oe/reset the 1/2/4 mbit xcfxxs platform flash proms in-system programming algorithm results in issuance of an internal device reset that causes oe/reset to pulse low. external programming xilinx reprogrammable proms ca n also be programmed by the xilinx multipro desktop tool or a third-party device programmer. this provides th e added flexibility of using pre-programmed devices with an in-system programmable option for future enhancements and design changes. xc3s1200e 3,832,320 xcf04s xc3s1600e 5,957,760 xcf08p spartan-3l xc3s1000l 3,223,488 xcf04s xc3s1500l 5,214,784 xcf08p xc3s5000l 13,271,936 xcf16p spartan-3 xc3s50 439,264 xcf01s xc3s200 1,047,616 xcf01s xc3s400 1,699,136 xcf02s xc3s1000 3,223,488 xcf04s xc3s1500 5,214,784 xcf08p xc3s2000 7,673,024 xcf08p xc3s4000 11,316,864 xcf16p xc3s5000 13,271,936 xcf16p spartan-iie xc2s50e 630,048 xcf01s xc2s100e 863,840 xcf01s xc2s150e 1,134,496 xcf02s xc2s200e 1,442,016 xcf02s xc2s300e 1,875,648 xcf02s xc2s400e 2,693,440 xcf04s xc2s600e 3,961,632 xcf04s spartan-ii xc2s15 197,696 xcf01s xc2s30 336,768 xcf01s xc2s50 559,200 xcf01s xc2s100 781,216 xcf01s xc2s150 1,040,096 xcf01s xc2s200 1,335,840 xcf02s notes: 1. if design revisioning or other advanced feature support is required, the xcfxxp can be used as an alternative to the xcf01s, xcf02s, or xcf04s. 2. assumes compression used. 3. the largest possible virtex-ii bitstream sizes are specified. refer to the virtex-ii user guide for information on bitgen options which affect bitstream size. ta bl e 3 : platform flash prom capacity platform flash prom configuration bits platform flash prom configuration bits xcf01s 1,048,576 xcf08p 8,388,608 xcf02s 2,097,152 xcf16p 16,777,216 xcf04s 4,194,304 xcf32p 33,554,432 ta bl e 2 : xilinx fpgas and compatible platform flash proms (continued) fpga configuration bitstream platform flash prom (1) figure 3: jtag in-system programming operation (a) solder device to pcb (b) program using download cable ds026_02_082703 gnd v cc (a) (b) platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 5 r reliability and endurance xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. each device meets all functional, performance, and data retention specifications within this endurance limit. design security the xilinx in-system programmable platform flash prom devices incorporate advanced data security features to fully protect the fpga programming data against unauthorized reading via jtag. the xc fxxp proms can also be programmed to prevent inadvertent writing via jtag. ta bl e 4 and ta b l e 5 show the security settings available for the xcfxxs prom and xcfxxp prom, respectively. read protection the read protect security bit can be set by the user to prevent the internal programming pattern from being read or copied via jtag. read protection does not prevent write operations. for the xcfxxs prom, the read protect security bit is set for the entire device, and resetting the read protect security bit requires erasing the entire device. for the xcfxxp prom the read protect security bit can be set for individual design revisions, and resetting the read protect bit requires erasing the particular design revision. write protection the xcfxxp prom device also allows the user to write protect (or lock) a particular design revision to prevent inadvertent erase or program operations. once set, the write protect security bit for an individual design revision must be reset (using the unlock command followed by isc_erase command) before an erase or program operation can be performed. ieee 1149.1 boundary-scan (jtag) the platform flash prom family is compatible with the ieee 1149.1 boundary-scan standard and the ieee 1532 in-system configuration standard. a test access port (tap) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by ieee std. 1149.1. in addition, the jtag interface is used to implement in-system programming (isp) to facilitate configuratio n, erasure, and verification operations on the platform flash prom device. ta bl e 6 , page 6 lists the required and optional boundary-scan instructions supported in the platform flash proms. refer to the ieee std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. caution! the xcfxxp jtag tap pause states are not fully compliant with the jtag 1149.1 specification. if a tempor ary pause of a jtag shift operation is required, then stop the jtag tck clock and maintain the jtag tap within the jtag shift-ir or shift-dr tap state. do not transition the xcfxxp jtag tap through the jtag pause-ir or pause-dr tap state to temporarily pause a jtag shift operation. instruction register the instruction register (ir) for the platform flash prom is connected between tdi and tdo during an instruction scan sequence. in preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. this pattern is shifted out onto tdo (lsb first), while an in struction is shifted into the instruction register from tdi. xcfxxs instruction register (8 bits wide) the instruction register (ir) for the xcfxxs prom is eight bits wide and is connected between tdi and tdo during an instruction scan sequence. the detailed composition of the instruction capture patt ern is illustrated in table 7, page 6 . the instruction capture pattern shifted out of the xcfxxs device includes ir[7:0]. ir[7:5] are reserved bits and are set to a logic 0. the isc status field, ir[4], contains logic 1 if the device is currently in in-system configuration (isc) mode; otherwise, it contains logic 0. the security field, ir[3], contains logic 1 if the device has been programmed with the security option turned on; otherwise, it contains ta b l e 4 : xcfxxs device data security options read protect read/verify inhibited program inhibited erase inhibited reset (default) set ? ta bl e 5 : xcfxxp design revision data security options read protect write protect read/verify inhibited program inhibited erase inhibited reset (default) reset (default) reset (default) set ?? set reset (default) ? set set ??? platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 6 r logic 0. ir[2] is unused, and is set to '0'. the remaining bits ir[1:0] are set to '01' as defined by ieee std. 1149.1. xcfxxp instruction register (16 bits wide) the instruction register (ir) for the xcfxxp prom is sixteen bits wide and is connected between tdi and tdo during an instruction scan sequence. the detailed composition of the instruction capt ure pattern is illustrated in table8, page6 . the instruction capture pattern shifted out of the xcfxxp device includes ir[15:0]. ir[15:9] are reserved bits and are set to a logic 0. the isc error field, ir[8:7], contains a 10 when an isc operation is a success; otherwise a 01 when an in-system configuration (isc) operation fails. the erase/program (er/prog) error field, ir[6:5], contains a 10 when an erase or program operation is a success; otherwise a 01 when an erase or program operation fails. the erase/program (er/prog) status field, ir[4], contains a logic 0 when the device is busy performing an erase or programming operation; otherwise, it contains a logic 1. the isc status field, ir[3], contains logic 1 if the device is currently in in-system configuration (isc) mode; otherwise, it contains logic 0. the done field, ir[2], contains logic 1 if the sampled design revision has been successfully programmed; otherwise, a logic 0 indicates incomplete programming. the remaining bits ir[1:0] are set to 01 as defined by i eee std. 1149.1. ta bl e 6 : platform flash prom boundary scan instructions boundary-scan command xcfxxs ir[7:0] (hex) xcfxxp ir[15:0] (hex) instruction description required instructions bypass ff ffff enables bypass sample/preload 01 0001 enables boundary-scan sample/preload operation extest 00 0000 enables boundary-scan extest operation optional instructions clamp fa 00fa enables boundary-scan clamp operation highz fc 00fc places all outputs in high-impedance state simultaneously idcode fe 00fe enables shifting out 32-bit idcode usercode fd 00fd enables shifting out 32-bit usercode platform flash prom specific instructions config ee 00ee initiates fpga configuration by pulsing cf pin low once. (for the xcfxxp this command also resets the selected design revision based on either the external rev_sel[1:0] pins or on the internal design revision selection bits.) (1) notes: 1. for more information see "initiating fpga configuration," page 13 . ta bl e 7 : xcfxxs instruction capture values loaded into ir as part of an instruction scan sequence tdi ir[7:5] ir[4] ir[3] ir[2] ir[1:0] tdo reserved isc status security 0 0 1 ta bl e 8 : xcfxxp instruction capture values loaded into ir as part of an instruction scan sequence tdi ir[15:9] ir[8:7] ir[6:5] ir[4] ir[3] ir[2] ir[1:0] tdo reserved isc error er/prog error er/prog status isc status done 0 1 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 7 r boundary scan register the boundary-scan register is used to control and observe the state of the device pins during the extest, sample/preload, and clamp in structions. each output pin on the platform flash prom has two register stages which contribute to the boundary-scan register, while each input pin has only one register stage. the bidirectional pins have a total of three register stages which contribute to the boundary-scan register. for each output pin, the register stage nearest to tdi controls and observes the output state, and the second stage closest to tdo controls and observes the high-z enable state of the output pin. for each input pin, a single register stage controls and observes the input state of the pin. the bidirectional pin combines the three bits, the input stage bit is first, followed by the output stage bit and finally the output enable stage bit. the output enable stage bit is closest to tdo. see the xcfxxs/xcfxxp pi n names and descriptions ta bl e s i n t h e "pinouts and pin descriptions," page 37 section for the boundary-scan bit order for all connected device pins, or see the appropriate bsdl file for the complete boundary-scan bit order description under the "attribute boundary_register" section in the bsdl file. the bit assigned to boundary-scan cell 0 is the lsb in the boundary-scan register, and is the register bit closest to tdo. identification registers idcode register the idcode is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. the idcode register is 32 bits wide. the idcode register can be shifted out for examination by using the idco de instruction. the idcode is available to any other system component via jtag. ta bl e 9 lists the idcode register values for the platform flash proms. the idcode register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the prom family code a = the specific platform flash prom product id c = the xilinx manufacturer's id the lsb of the idcode register is always read as logic 1 as defined by ieee std. 1149.1. usercode register the usercode instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents. by using the usercode instruction, a user-programmable identification code can be shifted out for examination. this code is loaded into the usercode register during programming of the platform flash prom. if the device is blank or was not loaded during programming, the usercode register contains ffffffffh . customer code register for the xcfxxp platform flash prom, in addition to the usercode, a unique 32-byte customer code can be assigned to each design revision enabled for the prom. the customer code is set during programming, and is typically used to supply information about the design revision contents. a private jtag instruction is required to read the customer code. if the prom is blank, or the customer code for the selected design revision was not loaded during programming, or if the particular design revision is erased, the custom er code will contain all ones. platform flash prom tap characteristics the platform flash prom family performs both in-system programming and ieee 1149.1 boundary-scan (jtag) testing via a single 4-wire test access port (tap). this simplifies system designs and allows standard automatic test equipment to perform both functions. the ac characteristics of the platform flash prom tap are described as follows. tap timing figure 4, page 8 shows the timing relationships of the tap signals. these tap timing characteristics are identical for both boundary-scan and isp operations. ta bl e 9 : idcodes assigned to platform flash proms device idcode (1) (hex) xcf01s < v >5044093 xcf02s < v >5045093 xcf04s < v >5046093 xcf08p < v >5057093 xcf16p < v >5058093 xcf32p < v >5059093 notes: 1. the < v > in the idcode field represents the device?s revision code (in hex) and may vary. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 8 r tap ac parameters ta bl e 1 0 shows the timing parameters for the tap waveforms shown in figure 4 . additional features for the xcfxxp internal oscillator the 8/16/32 mbit xcfxxp platform flash proms include an optional internal oscillator which can be used to drive the clkout and data pins on fpga configuration interface. the internal oscillator can be enabled when programming the prom, and the oscillator can be set to either the default frequency or to a slower frequency ( "xcfxxp prom as configuration master with in ternal oscillator as clock source," page 33 ). clkout the 8/16/32 mbit xcfxxp platform flash proms include the programmable option to enable the clkout signal which allows the prom to provide a source synchronous clock aligned to the data on the configuration interface. the clkout signal is derived from one of two clock sources: the clk input pin or the internal oscillator. the input clock source is selected during the prom programming sequence. output data is available on the rising edge of clkout. the clkout signal is enabled during programming, and is active when ce is low and oe/reset is high. on ce rising edge transition, if oe/reset is high and the prom terminal count has not been reached, then clkout remains active for an additional eights clock cycles before being disabled. on a oe/reset falling edge transition, clkout is immediately disabled. when disabled, the clkout pin is put into a high-impedance state and should be pulled high externally to provide a known state. when cascading platform flash proms with clkout enabled, after completing it's data transfer, the first prom disables clkout and drives the ceo pin enabling the next prom in the prom chain. the next prom will begin driving the clkout signal once that prom is enabled and data is available for transfer. during high-speed parallel configuration without compression, the fpga drives the busy signal on the configuration interface. when busy is asserted high, the proms internal address counter stops incrementing, and the current data value is held on the data outputs. while busy is high, the prom will c ontinue driving the clkout signal to the fpga, clocking the fpga?s configuration logic. figure 4: test access port timing tck t ckmin t mss tms tdi tdo t msh t dih t dov t dis ds026_04_020300 ta bl e 1 0 : test access port timing parameters symbol description min max units t ckmin tck minimum clock period when v ccj = 2.5v or 3.3v 100 ? ns t mss tms setup time when v ccj = 2.5v or 3.3v 10 ? ns t msh tms hold time when v ccj = 2.5v or 3.3v 25 ? ns t dis tdi setup time when v ccj = 2.5v or 3.3v 10 ? ns t dih tdi hold time when v ccj = 2.5v or 3.3v 25 ? ns t dov tdo valid delay when v ccj = 2.5v or 3.3v ? 30 ns platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 9 r when the fpga deasserts busy, indicating that it is ready to receive additional conf iguration data, the prom will begin driving new data onto the configuration interface. decompression the 8/16/32 mbit xcfxxp platform flash proms include a built-in data decompressor compatible with xilinx advanced compression technology. compressed platform flash prom files are created from the target fpga bitstream(s) using the impact software. only slave serial and slave selectmap (parallel) configuration modes are supported for fpga configuration when using a xcfxxp prom programmed with a compressed bitstream. compression rates will vary depending on several factors, including the target device family and the target design contents. the decompression option is enabled during the prom programming sequence. the prom decompresses the stored data before driving both clock and data onto the fpga's configuration interf ace. if decompression is enabled, then the platform flash clock output pin (clkout) must be used as the clock signal for the configuration interface, driving the target fpga's configuration clock input pin (cclk). either the prom's clk input pin or the internal o scillator must be selected as the source for clkout. any target fpga connected to the prom must operate as slave in the configuration chain, with the configuration mode set to slave serial mode or slave selectmap (parallel) mode. when decompression is enabled, the clkout signal becomes a controlled clock output with a reduced maximum frequency. when decompressed data is not ready, the clkout pin is put into a high-z state and must be pulled high externally to provide a known state. the busy input is automatically disabled when decompression is enabled. design revisioning design revisioning allows the user to create up to four unique design revisions on a single prom or stored across multiple cascaded proms. design revisioning is supported for the 8/16/32 mbit xcfxxp platform flash proms in both serial and parallel modes. design revisioning can be used with compressed prom files, and also when the clkout feature is enabled. the prom programming files along with the revision information files ( .cfi ) are created using the impact software. the .cfi file is required to enable design revision programming in impact. a single design revision is composed of from 1 to n 8-mbit memory blocks. if a single design revision contains less than 8 mbits of data, then the remaining space is padded with all ones. a larger design revision can span several 8-mbit memory blocks, and any space remaining in the last 8-mbit memory block is padded with all ones. ? a single 32-mbit prom contains four 8-mbit memory blocks, and can therefore store up to four separate design revisions: one 32-mbit design revision, two 16-mbit design revisions, three 8-mbit design revisions, four 8-mbit design revisions, and so on. ? because of the 8-mbit minimum size requirement for each revision, a single 16-mbit prom can only store up to two separate design revisions: one 16-mbit design revision, one 8-mbit design revision, or two 8-mbit design revisions. ? a single 8-mbit prom can store only one 8-mbit design revision. larger design revisions can be split over several cascaded proms. for example, two 32-mbit proms can store up to four separate design revisions: one 64-mbit design revision, two 32-mbit design revisions, three 16-mbit design revisions, four 16-mbit design revisions, and so on. when cascading one 16-mbit prom and one 8-mbit prom, there are 24 mbits of available space, and therefore up to three separate design revisions can be stored: one 24-mbit design revision, two 8-mbit design revisions, or three 8-mbit design revisions. see figure 5, page 10 for a few basic examples of how multiple revisions can be stored. the design revision partitioning is handled automatically during file generation in impact. during the prom file creation, each design revision is assigned a revision number: revision 0 = '00' revision 1 = '01' revision 2 = '10' revision 3 = '11' after programming the platform flash prom with a set of design revisions, a particul ar design revision can be selected using the external rev_sel[1:0] pins or using the internal programmable design revision control bits. the en_ext_sel pin determines if the external pins or internal bits are used to select the design revision. when en_ext_sel is low, design revision selection is controlled by the external revision select pins, rev_sel[1:0]. when en_ext_sel is high, design revision selection is controlled by the internal programmable revision select control bits. during power up, the design revision selection inputs (pins or control bits) are sampled internally. after power up, the design revision selection inputs are sampled again when any of the following events occur: ? on the rising edge of ce ? on the falling edge of oe/reset (when ce is low) ? on the rising edge of cf (when ce is low) ? when reconfiguration is initiated by using the jtag config instruction. the data from the selected design revision is then presented on the fpga configuration interface. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 10 r prom to fpga configuration mode and connections summary the fpga's i/o, logical functions, and internal interconnections are established by the configuration data contained in the fpga?s bitstream. the bitstream is loaded into the fpga either automatically upon power up, or on command, depending on the state of the fpga's mode pins. xilinx platform flash proms are designed to download directly to the fpga configuration interface. fpga configuration modes which are supported by the xcfxxs platform flash proms include: master serial and slave serial. fpga configuration modes which are supported by the xcfxxp platform flash proms include: master serial, slave serial, master selectmap, and slave selectmap. below is a short summary of the supported fpga configuration modes. see the respective fpga data sheet for device configurat ion details, including which configuration modes are supported by the targeted fpga device. fpga master serial mode in master serial mode, the fpga automatically loads the configuration bitstream in bit-serial form from external memory synchronized by the configuration clock (cclk) generated by the fpga. upon power-up or reconfiguration, the fpga's mode select pins are used to select the master serial configuration mode. master serial mode provides a simple configuration interface. only a serial data line, a clock line, and two control lines (init and done) are required to configure an fpga. data from the prom is read out sequentially on a single data line (din), accessed via the prom's internal address counter which is incremented on every valid rising edge of cclk. the serial bitstream data must be set up at the fpga?s din input pin a short time before each rising edge of the fpga's internally generated cclk signal. typically, a wide range of frequencies can be selected for the fpga?s internally generated cclk which always starts figure 5: design revision storage examples rev 0 (8 mbits) rev 1 (8 mbits) rev 2 (8 mbits) rev 3 (8 mbits) rev 0 (8 mbits) rev 1 (8 mbits) rev 2 (16 mbits) rev 0 (16 mbits) rev 1 (16 mbits) rev 0 (8 mbits) rev 1 (24 mbits) rev 0 (32 mbits) 4 design revisions 3 design revisions 2 design revisions 1 design revision (a) design revision storage examples for a single xcf32p prom rev 0 (16 mbits) rev 1 (16 mbits) rev 2 (16 mbits) rev 3 (16 mbits) rev 0 (16 mbits) rev 1 (16 mbits) rev 2 (32 mbits) rev 0 (32 mbits) rev 1 (32 mbits) rev 0 (16 mbits) rev 1 (16 mbits) rev 0 (32 mbits) 4 design revisions 3 design revisions 2 design revisions 1 design revision (b) design revision storage examples spanning two xcf32p proms prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 rev 0 (32 mbits) rev 1 (32 mbits) prom 1 prom 1 prom 1 prom 1 prom 1 ds123_20_102103 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 11 r at a slow default frequency. the fpga?s bitstream contains configuration bits which can switch cclk to a higher frequency for the remainder of the master serial configuration sequence. the desired cclk frequency is selected during bitstream generation. connecting the fpga device to the configuration prom for master serial configuration mode ( figure 6, page 14 ): ? the data output of the prom(s) drive the din input of the lead fpga device. ? the master fpga cclk output drives the clk input(s) of the prom(s) ? the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). ? the oe/reset pins of all proms are connected to the init_b pins of all fpga devices. this connection assures that the prom addre ss counter is reset before the start of any (re)configuration. ? the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( "dc characteristics over operating conditions," page 26 ). ? the prom cf pin is typically connected to the fpga's prog_b (or program ) input. for the xcfxxp only, the cf pin is a bidirectional pin. if the xcfxxp cf pin is not connected to the fpga's prog_b (or program ) input, then the pin should be tied high. fpga slave serial mode in slave serial mode, the fpga loads the configuration bitstream in bit-serial form from external memory synchronized by an externally supplied clock. upon power-up or reconfiguration, the fpga's mode select pins are used to select the slave serial configuration mode. slave serial mode provides a simple configuration interface. only a serial data line, a clock line, and two control lines (init and done) are required to configure an fpga. data from the prom is read out sequentially on a single data line (din), accessed via the prom's internal address counter which is incremented on every valid rising edge of cclk. the serial bitstream data must be set up at the fpga?s din input pin a short time before each rising edge of the externally provided cclk. connecting the fpga device to the configuration prom for slave serial configuration mode ( figure 7, page 15 ): ? the data output of the prom(s) drive the din input of the lead fpga device. ? the prom clkout (for xcfxxp only) or an external clock source drives the fpga's cclk input. ? the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). ? the oe/reset pins of all proms are connected to the init_b (or init) pins of all fpga devices. this connection assures that the prom address counter is reset before the start of any (re)configuration. ? the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( "dc characteristics over operating conditions," page 26 ). ? the prom cf pin is typically connected to the fpga's prog_b (or program ) input. for the xcfxxp only, the cf pin is a bidirectional pin. if the xcfxxp cf pin is not connected to the fpga's prog_b (or program ) input, then the pin should be tied high. serial daisy chain multiple fpgas can be daisy-chained for serial configuration from a single source. after a particular fpga has been configured, the data for the next device is routed internally to the fpga?s dout pin. typically the data on the dout pin changes on the fallin g edge of cclk, although for some devices the dout pin changes on the rising edge of cclk. consult the respective device data sheets for detailed information on a particular fpga device. for clocking the daisy-chained configuration, either the first fpga in the chain can be set to master serial, generating the cclk, with the remaining de vices set to slave serial ( figure 8, page 16 ), or all the fpga devices can be set to slave serial and an externally generated clock can be used to drive the fpga's configuration interface ( figure 7, page 15 or figure 12, page 20 ). fpga master selectmap (parallel) mode (xcfxxp prom only) in master selectmap mode, byte-wide data is written into the fpga, typically with a busy flag controlling the flow of data, synchronized by the configuration clock (cclk) generated by the fpga. upon power-up or reconfiguration, the fpga's mode select pins are used to select the master selectmap configuration mode. the configuration interface typically requires a parallel data bus, a clock line, and two control lines (init and done). in addition, the fpga?s chip select, write, and busy pins must be correctly controlled to enable selectmap configuration. the configuration data is read from the prom byte by byte on pins [d0..d7], accessed via the prom's internal address counter which is incremented on every valid rising edge of cclk. the bitstream data must be set up at the fpga?s [d0..d7] input pins a short time before each rising edge of the fpga's platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 12 r internally generated cclk signal. if busy is asserted (high) by the fpga, the configuration data must be held until busy goes low. an external data source or external pull-down resistors must be used to enable the fpga's active low chip select (cs or cs_b) and write (write or rdwr_b) signals to enable the fpga's selectmap configuration process. the master selectmap configuration interface is clocked by the fpga?s internal oscillator. typically, a wide range of frequencies can be selected for the internally generated cclk which always starts at a slow default frequency. the fpga?s bitstream contains configuration bits which can switch cclk to a higher frequency for the remainder of the master selectmap configuration sequence. the desired cclk frequency is selected during bitstream generation. after configuration, the pins of the selectmap port can be used as additional user i/o. alternatively, the port can be retained using the persist option. connecting the fpga device to the configuration prom for master selectmap (paralle l) configuration mode ( figure 9, page 17 ): ? the data outputs of the prom(s) drive the [d0..d7] input of the lead fpga device. ? the master fpga cclk output drives the clk input(s) of the prom(s) ? the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). ? the oe/reset pins of all proms are connected to the init_b pins of all fpga devices. this connection assures that the prom addre ss counter is reset before the start of any (re)configuration. ? the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( "dc characteristics over operating conditions," page 26 ). ? for high-frequency parallel configuration, the busy pins of all proms are connected to the fpga's busy output. this connection assures that the next data transition for the prom is delayed until the fpga is ready for the next configuration data byte. ? the prom cf pin is typically connected to the fpga's prog_b (or program ) input. for the xcfxxp only, the cf pin is a bidirectional pin. if the xcfxxp cf pin is not connected to the fpga's prog_b (or program ) input, then the pin should be tied high. fpga slave selectmap (parallel) mode (xcfxxp prom only) in slave selectmap mode, byte-wide data is written into the fpga, typically with a busy flag controlling the flow of data, synchronized by an externally supplied configuration clock (cclk). upon power-up or reconfiguration, the fpga's mode select pins are used to select the slave selectmap configuration mode. the configuration interface typically requires a parallel data bus, a clock line, and two control lines (init and done). in addition, t he fpga?s chip select, write, and busy pins must be correctly controlled to enable selectmap configuration. the conf iguration data is read from the prom byte by byte on pins [d0..d7], accessed via the prom's internal address counter which is incremented on every valid rising edge of cclk. the bitstream data must be set up at the fpga?s [d0..d7] input pins a short time before each rising edge of the provided cclk. if busy is asserted (high) by the fpga, the configuration data must be held until busy goes low. an external data source or external pull-down resistors must be used to enable the fpga's active low chip select (cs or cs_b) and write (write or rdwr_b) signals to enable the fpga's selectmap configuration process. after configuration, the pins of the selectmap port can be used as additional user i/o. alternatively, the port can be retained using the persist option. connecting the fpga device to the configuration prom for slave selectmap (parallel) configuration mode ( figure 10, page 18 ): ? the data outputs of the prom(s) drives the [d0..d7] inputs of the lead fpga device. ? the prom clkout (for xcfxxp only) or an external clock source drives the fpga's cclk input. ? the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). ? the oe/reset pins of all proms are connected to the init_b pins of all fpga devices. this connection assures that the prom address counter is reset before the start of any (re)configuration. ? the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( "dc characteristics over operating conditions," page 26 ). ? for high-frequency parallel configuration, the busy pins of all proms are connected to the fpga's busy output. this connection assures that the next data transition for the prom is delayed until the fpga is ready for the next configuration data byte. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 13 r ? the prom cf pin is typically connected to the fpga's prog_b (or program ) input. for the xcfxxp only, the cf pin is a bidirectional pin. if the xcfxxp cf pin is not connected to the fpga's prog_b (or program ) input, then the pin should be tied high. fpga selectmap (parallel) device chaining (xcfxxp prom only) multiple virtex-ii fpgas can be configured using the selectmap mode, and be made to start up simultaneously. to configure multiple devices in this way, wire the individual cclk, done, init, data ([d0..d7]), write (write or rdwr_b), and busy pins of all th e devices in parallel. if all devices are to be configured with the same bitstream, readback is not being used, and the cclk frequency selected does not require the use of the busy signal, the cs_b pins can be connected to a common line so all of the devices are configured simultaneously ( figure 10, page 18 ). with additional control logic, the individual devices can be loaded separately by asserting the cs_b pin of each device in turn and then enabling the appropriate configuration data. the prom can also store the individual bitstreams for each fpga for selectmap configuration in separate design revisions. when design revision ing is utilized, additional control logic can be used to select the appropriate bitstream by asserting the en_ext_sel pin, and using the rev_sel[1:0] pins to select the required bitstream, while asserting the cs_b pin for the fpga the bitstream is targeting ( figure 13, page 21 ). for clocking the parallel configuration chain, either the first fpga in the chain can be set to master selectmap, generating the cclk, with the remaining devices set to slave selectmap, or all the fpga devices can be set to slave selectmap and an externally generated clock can be used to drive the configuration interface. again, the respective device data sheets should be consulted for detailed information on a particular fpga device, including which configuration modes are supported by the targeted fpga device. cascading configuration proms when configuring multiple fpga s in a serial daisy chain, configuring multiple fpgas in a selectmap parallel chain, or configuring a single fpga requiring a larger configuration bitstream, cascaded proms provide additional memory ( figure 8, page 16 , figure 11, page 19 , figure 12, page 20 , and figure 13, page 21 ). multiple platform flash proms can be concatenated by using the ceo output to drive the ce input of the downstream device. the clock signal and the data outputs of all platform flash proms in the chain are interconnected. after the last data from the first prom is read, the first prom asserts its ceo output low and drives its outputs to a high-impedance state. the second prom recognizes the low level on its ce input and immediately enables its outputs. after configuration is complete, address counters of all cascaded proms are reset if the prom oe/reset pin goes low or ce goes high. when utilizing the advanced features for the xcfxxp platform flash prom, including the clock output (clkout) option, decompression option, or design revisioning, programming files which span cascaded prom devices can only be created for cascaded chains containing only xcfxxp proms. if the advanced features are not used, then cascaded prom chains can contain both xcfxxp and xcfxxs proms. initiating fpga configuration the options for initiating fpga configuration via the platform flash prom include: ? automatic configuration on power up ? applying an external prog_b (or program ) pulse ? applying the jtag config instruction following the fpga?s power-on sequence or the assertion of the prog_b (or program ) pin the fpga?s configuration memory is cleared, the configuration mode is selected, and the fpga is ready to accept a new configuration bitstream. the fpga?s prog_b pin can be controlled by an external source, or alternatively, the platform flash proms incorporate a cf pin that can be tied to the fpga?s prog_b pin. executing the config instruction through jtag pulses the cf output low once for 300-500 ns, resetting the fpga and initiating configuration. the impact software can issue the jtag config command to initiate fpga configuration by setting the "load fpga" option. when using the xcfxxp platform flash prom with design revisioning enabled, the cf pin should always be connected to the prog_b (or program ) pin on the fpga to ensure that the current design revision selection is sampled when the fpga is reset. the xcfxxp prom samples the current design revision selection from the external rev_sel pins or the internal programmable revision select bits on the rising edge of cf . when the jtag config command is executed, the xcfxxp will samp le the new design revision selection before initiating the fpga configuration sequence. when using the xcfxxp platform flash prom without design revisioning, if the cf pin is not connected to the fpga prog_b (or program ) pin, then the xcfxxp cf pin must be tied high. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 14 r configuration prom to fpga devi ce interface connection diagrams figure 6: configuring in master serial mode notes: 1 for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 for the xcfxxs the cf pin is an output pin. for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor. xilinx fpga master serial din cclk done init_b prog_b tdi tms tck gnd mode pins (1) dout tdo v ccj v cco v ccint din cclk done init_b prog_b din cclk done init_b prog_b 4.7 k 4.7 k (1) v cco (2) ...optional daisy-chained slave fpgas with different configurations ...optional slave fpgas with identical configurations tdi tms tck tdo platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d0 clk ce ceo oe/reset cf (3) tdo ds123_11_122105 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 15 r figure 7: configuring in slave serial mode notes: 1 for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 in slave serial mode, the configuration interface can be clocked by an external oscillator, or optionally?for the xcfxxp platform flash prom only?the clkout signal can be used to drive the fpga's configuration clock (cclk). if the xcfxxp prom's clkout signal is used, then clkout must be tied to a 4.7k resistor pulled up to v cco . 4 for the xcfxxs the cf pin is an output pin. for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor. xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck gnd mode pins (1) dout tdo v ccj v cco v ccint din cclk done init_b prog_b din cclk done init_b prog_b 4.7 k 4.7 k (1) v cco (2) ...optional daisy-chained slave fpgas with different configurations ...optional slave fpgas with identical configurations tdi tms tck tdo platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d0 clk (3) ce ceo oe/reset cf (4) tdo ds123_12_122105 external (3) oscillator platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 16 r figure 8: configuring multiple devices in master/slave serial mode notes: 1 for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 for the xcfxxs the cf pin is an output pin. for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor. platform flash prom first prom (prom 0) v ccint v cco (2) v ccj (2) tdi tms tck d0 clk ce ceo oe/reset cf (3) tdo xilinx fpga master serial din cclk done init_b prog_b tdi tms tck mode pins (1) dout tdo v ccj v cco v ccint 4.7 k 4.7 k (1) v cco (2) tdi tms tck tdo xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck d0 clk ce ceo oe/reset cf (3) tdo v ccj v cco v ccint mode pins (1) tdo ds123_13_122105 gnd gnd gnd gnd platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 17 r figure 9: configuring in master selectmap mode notes: 1 for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 cs_b (or cs) and rdwr_b (or write) must be either driven low or pulled down exernally. one option is shown. 4 the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high- frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. 5 for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor. xcfxxp platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk ce ceo oe/reset cf (5) busy (4) tdo xilinx fpga master selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd mode pins (1) rdwr_b cs_b tdo v ccj v cco v ccint d[0:7] cclk done init_b prog_b busy (4) 4.7 k 4.7 k (1) v cco (2) ...optional slave fpgas with identical configurations tdi tms tck tdo 1k 1k i/o (3) i/o (3) ds123_14_122105 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 18 r figure 10: configuring in slave selectmap mode notes: 1 for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 cs_b (or cs) and rdwr_b (or write) must be either driven low or pulled down externally. one option is shown. 4 the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high- frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. 5 in slave selectmap mode, the configuration interface can be clocked by an external oscillator, or, optionally, the clkout signal can be used to drive the fpga's configuration clock (cclk). if the xcfxxp prom's clkout signal is used, then clkout must be tied to a 4.7 k resistor pulled up to v cco . 6 for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor. xcfxxp platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk (5) ce ceo oe/reset cf (6) busy (4) tdo xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd mode pins (1) rdwr_b cs_b tdo v ccj v cco v ccint d[0:7] cclk done init_b prog_b busy (4) 4.7 k 4.7 k (1) v cco (2) ...optional slave fpgas with identical configurations tdi tms tck tdo 1k 1k i/o (3) i/o (3) ds123_15_122105 external (5) oscillator platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 19 r figure 11: configuring multiple devices with identical patterns in master/slave selectmap mode notes: 1 for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 cs_b (or cs) and rdwr_b (or write) must be either driven low or pulled down exernally. one option is shown. 4 the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high- frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. 5 for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor. xcfxxp platform flash prom first prom (prom 0) v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk ce ceo oe/reset cf (5) busy (4) tdo xilinx fpga master selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd mode pins (1) tdo v ccj v cco v ccint 4.7 k 4.7 k (1) v cco (2) tdi t ms tck t do xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd xcfxxp platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk ce ceo oe/reset cf (5) busy (4) tdo v ccj v cco v ccint mode pins (1) tdo ds123_16_122105 1k 1k i/o (3) i/o (3) 1k 1k i/o (3) i/o (3) rdwr_b cs_b rdwr_b cs_b platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 20 r figure 12: configuring multiple devices with desi gn revisioning in slave serial mode xcfxxp platform flash prom first prom (prom 0) v ccint v cco (2) v ccj (2) tdi tms tck en_ext_sel rev_sel[1:0] d0 clk (3) ce ceo oe/reset cf (4) tdo xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck v ccj v cco v ccint 4.7 k 4.7 k (1) v cco (2) tdi tms tck tdo xcfxxp platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck en_ext_sel rev_sel[1:0] d0 clk (3) ce ceo oe/reset cf (4) tdo v ccj v cco v ccint ds123_17_122105 design revision control logic en_ext_sel rev_sel[1:0] done cf / prog_b xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck mode pins (1) tdo gnd gnd gnd dout mode pins (1) gnd external (3) oscillator notes 1. for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2. for compatible voltages, refer to the appropriate data sheet. 3. in slave serial mode, the configuration interface can be clocked by an external oscillator, or optionally the clkout signal can be used to drive the fpga's configuration clock (cclk). if the xcfxxp prom's clkout signal is used, then clkout must be tied to a 4.7 k resistor pulled up to v cco . 4. for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 21 r figure 13: configuring multiple devices with de sign revisioning in slave selectmap mode notes: 1. for mode pin connections and done pin pull-up value, refer to the appropriate fpga data sheet. 2. for compatible voltages, refer to the appropriate data sheet. 3. rdwr_b (or write) must be either driven low or pulled down exernally. one option is shown. 4. the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. 5. in slave selectmap mode, the configuration interface can be clocked by an external oscillator, or optionally the clkout signal can be used to drive the fpga's configuration clock (cclk). if the xcfxxp prom's clkout signal is used, then it must be tied to a 4.7k resistor pulled up to v cco . 6 for the xcfxxp the cf pin is a bidirectional pin. for the xcfxxp, if cf is not connected to progb, then it must be tied to v cco via a 4.7 k pull-up resistor xcfxxp platform flash prom first prom (prom 0) vccint v cco (2) v ccj (2) tdi tms tck en_ext_sel rev_sel[1:0] gnd d[0:7] clk (5) ce ceo oe/reset cf (6) busy (4) tdo xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck mode pins (1) rdwr_b cs_b tdo v ccj v cco v ccint 4.7 k 4.7 k (1) v cco (2) tdi tms tck tdo xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck mode pins (1) rdwr_b cs_b tdo xcfxxp platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck en_ext_sel rev_sel[1:0] gnd d[0:7] clk (5) ce ceo oe/reset cf (6) busy (4) tdo v ccj v cco v ccint 1k i/o (3) 1k i/o (3) en_ext_sel rev_sel[1:0] cf done prog_b cs_b[1:0] design revision control logic gnd gnd ds123_18_122105 external (5) oscillator platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 22 r reset and power-on reset activation at power up, the device requires the v ccint power supply to monotonically rise to the nominal operating voltage within the specified v ccint rise time. if the power supply cannot meet this requirement, then the device might not perform power-on reset properly. during the power-up sequence, oe/reset is held low by the prom. once the required supplies have reached their respective por (power on reset) thresholds, the oe/reset release is delayed (t oer minimum) to allow more margin for the power supplies to stabilize before initiating configuration. the oe/reset pin is connected to an external 4.7k pull-up resistor and also to the target fpga's init pin. for systems utilizing slow-rising power supplies, an additional power monitoring circuit can be used to delay the target configuration until the system power reaches minimum operating voltages by holding the oe/reset pin low. when oe/reset is released, the fpga?s init pin is pulled high allowing the fpga's configuration sequence to begin. if the power drops below the power-down threshold (v ccpd ), the prom resets and oe/reset is again held low until the after the por threshold is reached. oe/reset polarity is not programmable. these power-up requirements are shown graphically in figure 14, page 22 . for a fully powered platform flash prom, a reset occurs whenever oe/reset is asserted (low) or ce is deasserted (high). the address counter is reset, ceo is driven high, and the remaining outputs are placed in a high-impedance state. notes: 1. the xcfxxs prom only requires v ccint to rise above its por threshold before releasing oe/reset . 2. the xcfxxp prom requires both v ccint to rise above its por threshold and for v cco to reach the recommended operating voltage level before releasing oe/reset . i/o input voltage tolerance and power sequencing the i/os on each re-programmable platform flash prom are fully 3.3v-tolerant. this allows 3v cmos signals to connect directly to the inputs without damage. the core power supply (v ccint ), jtag pin power supply (v ccj ), output power supply (v cco ), and external 3v cmos i/o signals can be applied in any order. additionally, for the xcfxxs prom only, when v cco is supplied at 2.5v or 3.3v and v ccint is supplied at 3.3v, the i/os are 5v-tolerant. this allows 5v cmos signals to connect directly to the inputs on a powered xcfxxs prom without damage. failure to power the prom correctly while supplying a 5v input signal may result in damage to the xcfxxs device. standby mode the prom enters a low-power standby mode whenever ce is deasserted (high). in standby mode, the address counter is reset, ceo is driven high, and the remaining outputs are placed in a high-impedance state regardless of the state of the oe/reset input. for the device to remain in the low-power standby mode, the jtag pins tms, tdi, and tdo must not be pulled low, and tck must be stopped (high or low). when using the fpga done signal to drive the prom ce pin high to reduce standby power after configuration, an external pull-up resistor should be used. typically a 330 figure 14: platform flash prom power-up requirements t oer v ccint v ccpor v ccpd 200 s r a mp 50 m s r a mp t oer t r s t time (m s ) a s low-r a mping v ccint su pply m a y s till b e b elow the minim u m oper a ting volt a ge when oe/re s et i s rele as ed. in thi s c as e, the config u r a tion s e qu ence m us t b e del a yed u ntil b oth v ccint a nd v cco h a ve re a ched their recommended oper a ting condition s . recommended operatin g ran g e delay or re s tart confi g uration d s 12 3 _21_10 3 10 3 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 23 r pull-up resistor is used, but refer to the appropriate fpga data sheet for the recommended done pin pull-up value. if the done circuit is connected to an led to indicate fpga configuration is complete, and is also connected to the prom ce pin to enable low-power standby mode, then an external buffer should be used to drive the led circuit to ensure valid transitions on the prom?s ce pin. if low-power standby mode is not required for the prom, then the ce pin should be connected to ground. ta bl e 1 1 : truth table for xcfxxs prom control inputs control inputs internal address outputs oe/reset ce data ceo icc high low if address < tc (2) : increment active high active if address = tc (2) : don't change high-z low reduced low low held reset high-z high active x (1) high held reset high-z high standby notes: 1. x = don?t care. 2. tc = terminal count = highest address value. ta bl e 1 2 : truth table for xcfxxp prom control inputs control inputs internal address outputs oe/reset ce cf busy (5) data ceo clkout icc high low high low if address < tc (2) and address < ea (3) : increment active high active active if address < tc (2) and address = ea (3) : don't change high-z high high-z reduced else if address = tc (2) : don't change high-z low high-z reduced high low high high unchanged active and unchanged high active active high low x (1) reset (4) active high active active low low x x held reset (4) high-z high high-z active x high x x held reset (4) high-z high high-z standby notes: 1. x = don?t care. 2. tc = terminal count = highest address value. 3. for the xcfxxp with design revisioning enabled, ea = end address (last address in the selected design revision). 4. for the xcfxxp with design revisioning enabled, reset = address reset to the beginning address of the selected bank. if desig n revisioning is not enabled, then reset = address reset to address 0. 5. the busy input is only enabled when the xcfxxp is programmed for parallel data output and decompression is not enabled. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 24 r dc electrical characteristics absolute maximum ratings supply voltage requirements for power-on reset and power-down symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units v ccint internal supply voltage relative to gnd ?0.5 to +4.0 ?0.5 to +2.7 v v cco i/o supply voltage relative to gnd ?0.5 to +4.0 ?0.5 to +4.0 v v ccj jtag i/o supply voltage relative to gnd ?0.5 to +4.0 ?0.5 to +4.0 v v in input voltage with respect to gnd v cco < 2.5v ?0.5 to +3.6 ?0.5 to +3.6 v v cco 2.5v ?0.5 to +5.5 ?0.5 to +3.6 v v ts voltage applied to high-z output v cco < 2.5v ?0.5 to +3.6 ?0.5 to +3.6 v v cco 2.5v ?0.5 to +5.5 ?0.5 to +3.6 v t stg storage temperature (ambient) ?65 to +150 ?65 to +150 c t j junction temperature +125 +125 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, t he device pins can undershoot to ?2.0v or overshoot to +7.0v, provided th is over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time adversely affects device reliability. 3. for soldering guidelines, see the information on "packaging and thermal characteristics" at www.xilinx.com. symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units min max min max t vcc v ccint rise time from 0v to nominal voltage (2) 0.2500.250ms v ccpor por threshold for the v ccint supply 1 ? 0.5 ? v t oer oe/reset release delay following por (3) 0.5 3 0.5 30 ms v ccpd power-down threshold for v ccint supply ? 1 ? 0.5 v t rst time required to trigger a device reset when the v ccint supply drops below the maximum v ccpd threshold 10 ? 10 ? ms notes: 1. v ccint , v cco , and v ccj supplies may be applied in any order. 2. at power up, the device requires the v ccint power supply to monotonically rise to the nominal operating voltage within the specified t vcc rise time. if the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. see figure 14, page 22 . 3. if the v ccint and v cco supplies do not reach their respective recommended operating conditions before the oe/reset pin is released, then the configuration data from the prom will not be available at the recommended threshold levels. the configuration sequence must be delayed until both v ccint and v cco have reached their recommended operating conditions. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 25 r recommended operating conditions quality and reliability characteristics symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units min typ max min typ max v ccint internal voltage supply 3.0 3.3 3.6 1.65 1.8 2.0 v v cco supply voltage for output drivers 3.3v operation 3.0 3.3 3.6 3.0 3.3 3.6 v 2.5v operation 2.3 2.5 2.7 2.3 2.5 2.7 v 1.8v operation 1.7 1.8 1.9 1.7 1.8 1.9 v 1.5v operation ? ? ? tbd 1.5 tbd v v ccj supply voltage for jtag output drivers 3.3v operation 3.0 3.3 3.6 3.0 3.3 3.6 v 2.5v operation 2.3 2.5 2.7 2.3 2.5 2.7 v v il low-level input voltage 3.3v operation 0 ? 0.8 0 ? 0.8 v 2.5v operation 0 ? 0.7 0 ? 0.7 v 1.8v operation ? ? 20% v cco ??20% v cco v 1.5v operation ? ? ? 0 ? tbd v v ih high-level input voltage 3.3v operation 2.0 ? 5.5 2.0 ? 3.6 v 2.5v operation 1.7 ? 5.5 1.7 ? 3.6 v 1.8v operation 70% v cco ? 3.6 70% v cco ?3.6v 1.5v operation ? ? ? tbd ? 3.6 v t in input signal transition time (1) ? ?500? ?500ns v o output voltage 0 ? v cco 0?v cco v t a operating ambient temperature ?40 ? 85 ?40 ? 85 c notes: 1. input signal transition time measured between 10% v cco and 90% v cco . symbol description min max units t dr data retention 20 ? years n pe program/erase cycles (endurance) 20,000 ? cycles v esd electrostatic discharge (esd) 2,000 ? volts platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 26 r dc characteristics over operating conditions symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units test conditions min max test conditions min max v oh high-level output voltage for 3.3v outputs i oh = ?4 ma 2.4 ? i oh = ?4 ma 2.4 ? v high-level output voltage for 2.5v outputs i oh = ?500 a v cco ? 0.4 ? i oh = ?500 a v cco ? 0.4 ? v high-level output voltage for 1.8v outputs i oh = ?50 a v cco ? 0.4 ? i oh = ?50 a v cco ? 0.4 ? v high-level output voltage for 1.5v outputs ? ? ? i oh = tbd tbd ? v v ol low-level output voltage for 3.3v outputs i ol = 4 ma ? 0.4 i ol = 4 ma ? 0.4 v low-level output voltage for 2.5v outputs i ol = 500 a?0.4i ol = 500 a?0.4 v low-level output voltage for 1.8v outputs i ol = 50 a?0.4i ol = 50 a?0.4 v low-level output voltage for 1.5v outputs ? ? ? i ol = tbd ? tbd v i ccint internal voltage supply current, active mode 33 mhz ? 10 33 mhz ? 10 ma i cco (1) output driver supply current, active serial mode 33 mhz ? 10 33 mhz ? 10 ma output driver supply current, active parallel mode ? ? ? 33 mhz ? 40 ma i ccj jtag supply current, active mode note (2) ? 5 note (2) ? 5 ma i ccints internal voltage supply current, standby mode note (3) ? 5 note (3) ? 1 ma i ccos output driver supply current, standby mode note (3) ? 1 note (3) ? 1 ma i ccjs jtag supply current, standby mode note (3) ? 1 note (3) ? 1 ma i ilj jtag pins tms, tdi, and tdo pull-up current v ccj = max v in = gnd ?100 v ccj = max v in = gnd ?100 a i il input leakage current v ccint = max v cco = max v in = gnd or v cco ?10 10 v ccint = max v cco = max v in = gnd or v cco ?10 10 a i ih input and output high-z leakage current v ccint = max v cco = max v in = gnd or v cco ?10 10 v ccint = max v cco = max v in = gnd or v cco ?10 10 a i ilp source current through internal pull-ups on en_ext_sel , rev_sel0, rev_sel1 ??? v ccint = max v cco = max v in = gnd or v cco ?100 a i ihp sink current through internal pull-down on busy ? ? ? v ccint = max v cco = max v in = gnd or v cco -100 ? a c in input capacitance v in = gnd f = 1.0 mhz ?8 v in = gnd f = 1.0 mhz ?8pf c out output capacitance v in = gnd f = 1.0 mhz ?14 v in = gnd f = 1.0 mhz ?14pf notes: 1. output driver supply current specification based on no load conditions. 2. tdi/tms/tck non-static (active). 3. ce high, oe low, and tms/tdi/tck static. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 27 r ac electrical characteristics ac characteristics over operating conditions xcfxxs and xcfxxp prom as configuration slave with clk input pin as clock source symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units min max min max t hcf cf hold time to guarantee design revision selection is sampled when v cco = 3.3v or 2.5v (9) 300 300 ns cf hold time to guarantee design revision selection is sampled when v cco = 1.8v (9) 300 300 ns t cf cf to data delay when vcco = 3.3v or 2.5v (8) ???25ns cf to data delay when vcco = 1.8v (8) ???25ns t oe oe/reset to data delay (6) when v cco = 3.3v or 2.5v ? 10 ? 25 ns oe/reset to data delay (6) when v cco = 1.8v ?30?25ns t ce ce to data delay (5) when v cco = 3.3v or 2.5v ? 15 ? 25 ns ce to data delay (5) when v cco = 1.8v ?30?25ns t cac clk to data delay (7) when v cco = 3.3v or 2.5v ? 15 ? 25 ns clk to data delay (7) when v cco = 1.8v ?30?25ns t oh data hold from ce , oe/reset , clk, or cf when v cco = 3.3v or 2.5v (8) 0?5?ns data hold from ce , oe/reset , clk, or cf when v cco = 1.8v (8) 0?5?ns ce oe/re s et clk bu s y (option a l) data t ce t lc t hc t s ce t oe t cac t hce t hoe t cyc t oh t df t oh t hb t s b cf en_ext_ s el rev_ s el[1:0] t s xt t hxt t s rv t hrv d s 12 3 _22_122905 t s xt t hxt t s rv t hrv t cf t hcf platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 28 r t df ce or oe/reset to data float delay (2) when v cco = 3.3v or 2.5v ?25?45ns ce or oe/reset to data float delay (2) when v cco = 1.8v ?30?45ns t cyc clock period (6) (serial mode) when v cco = 3.3v or 2.5v 30 ? 25 ? ns clock period (6) (serial mode) when v cco = 1.8v 67 ? 25 ? ns clock period (6) (parallel mode) when v cco = 3.3v or 2.5v ? ? 30 ? ns clock period (6) (parallel mode) when v cco = 1.8v ? ? 30 ? ns t lc clk low time (3) when v cco = 3.3v or 2.5v 10 ? 12 ? ns clk low time (3) when v cco = 1.8v 15 ? 12 ? ns t hc clk high time (3) when v cco = 3.3v or 2.5v 10 ? 12 ? ns clk high time (3) when v cco = 1.8v 15 ? 12 ? ns t sce ce setup time to clk (guarantees proper counting) (3) when v cco = 3.3v or 2.5v 20?30?ns ce setup time to clk (guarantees proper counting) (3) when v cco = 1.8v 30 30 ? ns t hce ce hold time (guarantees counters are reset) (5) when v cco = 3.3v or 2.5v 250 ? 2000 ? ns ce hold time (guarantees counters are reset) (5) when v cco = 1.8v 250 ? 2000 ? ns t hoe oe/reset hold time (guarantees counters are reset) (6) when v cco = 3.3v or 2.5v 250 ? 2000 ? ns oe/reset hold time (guarantees counters are reset) (6) when v cco = 1.8v 250 ? 2000 ? ns t sb busy setup time to clk when v cco = 3.3v or 2.5v (8) ??12?ns busy setup time to clk when v cco = 1.8v (8) ??12?ns t hb busy hold time to clk when v cco = 3.3v or 2.5v (8) ??8?ns busy hold time to clk when v cco = 1.8v (8) ??8?ns t sxt en_ext_sel setup time to cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) ? ? 300 ? ns en_ext_sel setup time to cf, ce or oe/reset when v cco = 1.8v (8) ? ? 300 ? ns t hxt en_ext_sel hold time from cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) ? ? 300 ? ns en_ext_sel hold time from cf, ce or oe/reset when v cco = 1.8v (8) ? ? 300 ? ns t srv rev_sel setup time to cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) ? ? 300 ? ns rev_sel setup time to cf, ce or oe/reset when v cco = 1.8v (8) ? ? 300 ? ns symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units min max min max platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 29 r t hrv rev_sel hold time from cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) ? ? 300 ? ns rev_sel hold time from cf, ce or oe/reset when v cco = 1.8v (8) ? ? 300 ? ns notes: 1. ac test load = 50 pf for xcf01s/xcf02 s/xcf04s; 30 pf for xcf08p/xcf16p/xcf32p. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady-state active levels. 3. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 4. if t hce high < 2 s, t ce = 2 s. 5. if t hoe low < 2 s, t oe = 2 s. 6. this is the minimum possible t cyc . actual t cyc = t cac + fpga data setup time. example: with the xcf32p in serial mode with v cco at 3.3v, if fpga data setup time = 15 ns, then the actual t cyc = 25 ns +15 ns = 40 ns. 7. guaranteed by design; not tested. 8. cf , en_ext_sel , rev_sel[1:0], and busy are inputs for the xcfxxp prom only. 9. when jtag config command is issued, prom will drive cf low for at least the t hcf minimum. symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units min max min max platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 30 r xcfxxp prom as configuration master with clk input pin as clock source symbol description xcf08p, xcf16p, xcf32p units min max t hcf cf hold time to guarantee design revision selection is sampled when v cco = 3.3v or 2.5v (11) 300 300 cf hold time to guarantee design revision selection is sampled when v cco = 1.8v (11) 300 300 t cf cf to data delay when vcco = 3.3v or 2.5v ? tbd ns cf to data delay when vcco = 1.8v ? tbd ns t oe oe/reset to data delay (6) when v cco = 3.3v or 2.5v ? 25 ns oe/reset to data delay (6) when v cco = 1.8v ? 25 ns t ce ce to data delay (5) when v cco = 3.3v or 2.5v ? 25 ns ce to data delay (5) when v cco = 1.8v ? 25 ns t eoh data hold from ce , oe/reset , or cf when v cco = 3.3v or 2.5v 5 ? ns data hold from ce , oe/reset , or cf when v cco = 1.8v 5 ? ns t df ce or oe/reset to data float delay (2) when v cco = 3.3v or 2.5v ? 45 ns ce or oe/reset to data float delay (2) when v cco = 1.8v ? 45 ns t oecf oe/reset to clkout float delay (2) when v cco = 3.3v or 2.5v ? tbd ns oe/reset to clkout float delay (2) when v cco = 1.8v ? tbd ns t cecf ce to clkout float delay (2) when v cco = 3.3v or 2.5v ? tbd ns ce to clkout float delay (2) when v cco = 1.8v ? tbd ns ce oe/re s et clk clkout bu s y (option a l) data t ce t lc t hc t oe t hce t hoe t cyco t hb t s b t oecc t cecc t clko t coh t ccdd d s 12 3 _25_122905 t eoh t df note: 8 clkout cycle s a re o u tp u t a fter ce ri s ing edge, b efore clkout tri s t a te s , if oe/re s et rem a in s high, a nd termin a l co u nt h as not b een re a ched. cf en_ext_ s el rev_ s el[1:0] t s xt t hxt t s rv t hrv t s xt t hxt t s rv t hrv t cf t cfcc t cecf t oecf t ddc t hcf platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 31 r t cyco clock period (7) (serial mode) when v cco = 3.3v or 2.5v 30 ? ns clock period (7) (serial mode) when v cco = 1.8v 30 ? ns clock period (7) (parallel mode) when v cco = 3.3v or 2.5v 35 ? ns clock period (7) (parallel mode) when v cco = 1.8v 35 ? ns t lc clk low time (3) when v cco = 3.3v or 2.5v 12 ? ns clk low time (3) when v cco = 1.8v 12 ? ns t hc clk high time (3) when v cco = 3.3v or 2.5v 12 ? ns clk high time (3) when v cco = 1.8v 12 ? ns t hce ce hold time (guarantees counters are reset) (5) when v cco = 3.3v or 2.5v 2000 ? ns ce hold time (guarantees counters are reset) (5) when v cco = 1.8v 2000 ? ns t hoe oe/reset hold time (guarantees counters are reset) (6) when v cco = 3.3v or 2.5v 2000 ? ns oe/reset hold time (guarantees counters are reset) (6) when v cco = 1.8v 2000 ? ns t sb busy setup time to clkout when v cco = 3.3v or 2.5v 12 ? ns busy setup time to clkout when v cco = 1.8v 12 ? ns t hb busy hold time to clkout when v cco = 3.3v or 2.5v 8 ? ns busy hold time to clkout when v cco = 1.8v 8 ? ns t clko clk input to clkout output delay when v cco = 3.3v or 2.5v ? 35 ns clk input to clkout output delay when v cco = 1.8v ? 35 ns clk input to clkout output delay when v cco = 3.3v or 2.5v with decompression (12) ?35ns clk input to clkout output delay when v cco = 1.8v with decompression (12) ?35ns t cecc ce to clkout delay (8) when v cco = 3.3v or 2.5v 0 2 clk cycles ? ce to clkout delay (8) when v cco = 1.8v 0 2 clk cycles ? t oecc oe/reset to clkout delay (8) when v cco = 3.3v or 2.5v 02 clk cycles ? oe/reset to clkout delay (8) when v cco = 1.8v 02 clk cycles ? t cfcc cf to clkout delay (8) when v cco = 3.3v or 2.5v 0 tbd ? cf to clkout delay (8) when v cco = 1.8v 0 tbd ? t ccdd clkout to data delay when v cco = 3.3v or 2.5v (9) ?30ns clkout to data delay when v cco = 1.8v (9) ?30ns t ddc data setup time to clkout when v cco = 3.3v or 2.5v with decompression (9)(12) 5ns data setup time to clkout when v cco = 1.8v with decompression (9)(12) 5ns t coh data hold from clkout when v cco = 3.3v or 2.5v 3 ? ns data hold from clkout when v cco = 1.8v 3 ? ns data hold from clkout when v cco = 3.3v or 2.5v with decompression (12) 3?ns data hold from clkout when v cco = 1.8v with decompression (12) 3?ns t sxt en_ext_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns symbol description xcf08p, xcf16p, xcf32p units min max platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 32 r t hxt en_ext_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t srv rev_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t hrv rev_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns notes: 1. ac test load = 50 pf for xcf01s/xcf02 s/xcf04s; 30 pf for xcf08p/xcf16p/xcf32p. 2. float delays are measured with 5 pf ac loads.transition is measured at 200 mv from steady-state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 s, t ce = 2 s. 6. if t hoe low < 2 s, t oe = 2 s. 7. this is the minimum possible t cyco . actual t cyco = t ccdd + fpga data setup time. example: with the xcf32p in serial mode with v cco at 3.3v, if fpga data setup time = 15 ns, then the actual t cyco = 25 ns +15 ns = 40 ns. 8. the delay before the enabled clkout signal begins clocking data out of the device is dependent on the clocking configuration. the delay before clkout is enabled will increase if decompression is enabled. 9. slower clk frequency option may be required to meet the fpga data sheet setup time. 10. when decompression is enabled, the clkout signal becomes a controlled clock output. when decompressed data is available, clk out will toggle at ? the source clock frequency (either ? the selected internal clock frequency or ? the external clk input frequen cy). when decompressed data is not available, the clkout pin is parked high. if clkout is used, then it must be pulled high externally us ing a 4.7k pull-up to v cco . 11. when jtag config command is issued, prom will drive cf low for at least the t hcf minimum. symbol description xcf08p, xcf16p, xcf32p units min max platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 33 r xcfxxp prom as configuration master with internal oscillator as clock source symbol description xcf08p, xcf16p, xcf32p units min max t hcf cf hold time to guarantee design revision selection is sampled when v cco = 3.3v or 2.5v (12) 300 300 cf hold time to guarantee design revision selection is sampled when v cco = 1.8v (12) 300 300 t cf cf to data delay when vcco = 3.3v or 2.5v ? tbd ns cf to data delay when vcco = 1.8v ? tbd ns t oe oe/reset to data delay (6) when v cco = 3.3v or 2.5v ? 25 ns oe/reset to data delay (6) when v cco = 1.8v ? 25 ns t ce ce to data delay (5) when v cco = 3.3v or 2.5v ? 25 ns ce to data delay (5) when v cco = 1.8v ? 25 ns t eoh data hold from ce , oe/reset , or cf when v cco = 3.3v or 2.5v 5 ? ns data hold from ce , oe/reset , or cf when v cco = 1.8v 5 ? ns t df ce or oe/reset to data float delay (2) when v cco = 3.3v or 2.5v ? 45 ns ce or oe/reset to data float delay (2) when v cco = 1.8v ? 45 ns t oecf oe/reset to clkout float delay (2) when v cco = 3.3v or 2.5v ? tbd ns oe/reset to clkout float delay (2) when v cco = 1.8v ? tbd ns t cecf ce to clkout float delay (2) when v cco = 3.3v or 2.5v ? tbd ns ce to clkout float delay (2) when v cco = 1.8v ? tbd ns t hce ce hold time (guarantees counters are reset) (5) when v cco = 3.3v or 2.5v 2000 ? ns ce hold time (guarantees counters are reset) (5) when v cco = 1.8v 2000 ? ns ce oe/re s et clkout bu s y (option a l) data t ce t oe t hce t hoe t hb t s b t oec t cec t coh t cdd d s 12 3 _26_122905 t eoh t df note: 8 clkout cycle s a re o u tp u t a fter ce ri s ing edge, b efore clkout tri s t a te s , if oe/re s et rem a in s high, a nd termin a l co u nt h as not b een re a ched. cf en_ext_ s el rev_ s el[1:0] t s xt t hxt t s rv t hrv t s xt t hxt t s rv t hrv t cf t cfc t cecf t oecf t ddc t hcf platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 34 r t hoe oe/reset hold time (guarantees counters are reset) (6) when v cco = 3.3v or 2.5v 2000 ? ns oe/reset hold time (guarantees counters are reset) (6) when v cco = 1.8v 2000 ? ns t sb busy setup time to clkout when v cco = 3.3v or 2.5v 12 ? ns busy setup time to clkout when v cco = 1.8v 12 ? ns t hb busy hold time to clkout when v cco = 3.3v or 2.5v 8 ? ns busy hold time to clkout when v cco = 1.8v 8 ? ns t cec ce to clkout delay (7) when v cco = 3.3v or 2.5v 0 1 s ce to clkout delay (7) when v cco = 1.8v 0 1 s t oec oe/reset to clkout delay (7) when v cco = 3.3v or 2.5v 0 1 s oe/reset to clkout delay (7) when v cco = 1.8v 0 1 s t cfc cf to clkout delay (7) when v cco = 3.3v or 2.5v 0 tbd ? cf to clkout delay (7) when v cco = 1.8v 0 tbd ? t cdd clkout to data delay when v cco = 3.3v or 2.5v (8) ?30ns clkout to data delay when v cco = 1.8v (8) ?30ns t ddc data setup time to clkout when v cco = 3.3v or 2.5v with decompression (8)(11) 5ns data setup time to clkout when v cco = 1.8v with decompression (8)(11) 5ns t coh data hold from clkout when v cco = 3.3v or 2.5v 3 ? ns data hold from clkout when v cco = 1.8v 3 ? ns data hold from clkout when v cco = 3.3v or 2.5v with decompression (11) 3?ns data hold from clkout when v cco = 1.8v with decompression (11) 3?ns t sxt en_ext_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t hxt en_ext_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t srv rev_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t hrv rev_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns f f clkout default (fast) frequency (9) 25 50 mhz clkout default (fast) frequency with decompression (11) 12.5 25 mhz symbol description xcf08p, xcf16p, xcf32p units min max platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 35 r f s clkout alternate (slower) frequency (10) 12.5 25 mhz clkout alternate (slower) frequency with decompression (11) 6 12.5 mhz notes: 1. ac test load = 50 pf for xcf01s/xcf02 s/xcf04s; 30 pf for xcf08p/xcf16p/xcf32p. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady-state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 s, t ce = 2 s. 6. if t hoe low < 2 s, t oe = 2 s. 7. the delay before the enabled clkout signal begins clocking data out of the device is dependent on the clocking configuration. the delay before clkout is enabled will increase if decompression is enabled. 8. slower clk frequency option may be required to meet the fpga data sheet setup time. 9. typical clkout default (fast) period = 25 ns (40 mhz) 10. typical clkout alternate (slower) period = 50 ns (20 mhz) 11. when decompression is enabled, the clkout signal becomes a controlled clock output. when decompressed data is available, clk out will toggle at ? the source clock frequency (either ? the selected internal clock frequency or ? the external clk input frequen cy). when decompressed data is not available, the clkout pin is parked high. if clkout is used, then it must be pulled high externally us ing a 4.7k pull-up to v cco . 12. when jtag config command is issued, prom will drive cf low for at least the t hcf minimum. symbol description xcf08p, xcf16p, xcf32p units min max platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 36 r ac characteristics over operat ing conditions when cascading symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, xcf32p units min max min max t cdf clk to output float delay (2,3) when v cco = 2.5v or 3.3v ? 25 ? 20 ns clk to output float delay (2,3) when v cco = 1.8v ? 35 ? 20 ns t ock clk to ceo delay (3,5) when v cco = 2.5v or 3.3v ? 20 ? 20 ns clk to ceo delay (3,5) when v cco = 1.8v ? 35 ? 20 ns t oce ce to ceo delay (3,6) when v cco = 2.5v or 3.3v ? 20 ? 80 ns ce to ceo delay (3,6) when v cco = 1.8v ? 35 ? 80 ns t ooe oe/reset to ceo delay (3) when v cco = 2.5v or 3.3v ? 20 ? 80 ns oe/reset to ceo delay (3) when v cco = 1.8v ? 35 ? 80 ns t coce clkout to ceo delay when v cco = 2.5v or 3.3v ? ? ? 20 ns clkout to ceo delay when v cco = 1.8v ? ? ? 20 ns t codf clkout to output float delay when v cco = 2.5v or 3.3v ? ? ? 25 ns clkout to output float delay when v cco = 1.8v ? ? ? 25 ns notes: 1. ac test load = 50 pf for xcf01s/xcf02s/ xcf04s; 30 pf for xcf08p/xcf16p/xcf32p. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. for cascaded proms, if the fpga?s dual-purpose configuration da ta pins are set to persist as configuration pins, the minimum period is increased based on the clk to ceo and ce to data propagation delays: - t cyc minimum = t ock + t ce + fpga data setup time. - t cac maximum = t ock + t ce 6. for cascaded proms, if the fpga?s dual-purpose configuration da ta pins become general i/o pins after configuration; to allow for the disable to propagate to the cascaded proms and to avoid c ontention on the data lines followi ng configuration, the minimum period is increased based on the ce to ceo and ce to data propagation delays: - t cyc minimum = t oce + t ce - t cac maximum = t ock + t ce oe/reset ce clk clkout (optional) data ceo t oce t ooe first bit last bit t cdf t codf t ock t coce ds123_23_102203 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 37 r pinouts and pin descriptions the xcfxxs platform flash prom is available in the vo20 and vog20 packages. the xcfxxp platform flash prom is available in the vo48, vog48, fs48, and fsg48 packages. notes: 1. vo20/vog20 denotes a 20-pin (tssop) plastic thin shrink small outline package 2. vo48/vog48 denotes a 48-pin (tsop) plastic thin small outline package. 3. fs48/fsg48 denotes a 48-pin (tfbga) plastic th in fine pitch ball grid array (0.8 mm pitch). xcfxxs pinouts and pin descriptions xcfxxs vo20/vog20 pin names and descriptions ta bl e 1 3 provides a list of the pin names and descript ions for the xcfxxs 20-pin vo20/vog20 package. ta bl e 1 3 : xcfxxs pin names and descriptions pin name boundary scan order boundary scan function pin description 20-pin tssop (vo20/vog20) d0 4 data out d0 is the data output pin to provide data for configuring an fpga in serial mode. the d0 output is set to a high-impedance state during ispen (when not clamped). 1 3 output enable clk 0 data in configuration clock input. each rising edge on the clk input increments the internal address counter if the clk input is selected, ce is low, and oe/reset is high. 3 oe/reset 20 data in output enable/reset (open-drain i/o). when low, this input holds the address counter reset and the data output is in a high-impedance state. this is a bidirectional open-drain pin that is held low while the pr om completes the internal power-on reset sequence. polarity is not programmable. 8 19 data out 18 output enable ce 15 data in chip enable input. when ce is high, the device is put into low-power standby mode, the address counter is reset, and the data pins are put in a high-impedance state. 10 cf 22 data out configuration pulse (open-drain output). allows jtag config instruction to initiate fpga configuration without powering down fpga. this is an open-drain output that is pulsed low by the jtag config command. 7 21 output enable ceo 12 data out chip enable output. chip enable output (ceo ) is connected to the ce input of the next prom in the chain. this output is low when ce is low and oe/reset input is high, and the internal address counter has been incremented beyond its terminal count (tc) value. ceo returns to high when oe/reset goes low or ce goes high. 13 11 output enable tms mode select jtag mode select input. the st ate of tms on the rising edge of tck determines the state transitions at the test access port (tap) controller. tms has an internal 50 k resistive pull-up to v ccj to provide a logic 1 to the device if the pin is not driven. 5 tck clock jtag clock input. this pin is the jtag test clock. it sequences the tap controller and all the jtag test and programming electronics. 6 tdi data in jtag serial data input. this pin is the serial input to all jtag instruction and data registers. tdi has an internal 50 k resistive pull-up to v ccj to provide a logic 1 to the device if the pin is not driven. 4 tdo data out jtag serial data output. this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50 k resistive pull-up to v ccj to provide a logic 1 to the system if the pin is not driven. 17 vccint +3.3v supply. positive 3.3v supply voltage for internal logic. 18 platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 38 r xcfxxs vo20/vog20 pinout diagram vcco +3.3v, 2.5v, or 1.8v i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the output voltage drivers and input buffers. 19 vccj +3.3v or 2.5v jtag i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the tdo output voltage driver and tck, tms, and tdi input buffers. 20 gnd ground 11 dnc do not connect. (these pins must be left unconnected.) 2 , 9, 12, 14, 15, 16 figure 15: vo20/vog20 pinout diagram (top view) with pin names ta bl e 1 3 : xcfxxs pin names and descriptions pin name boundary scan order boundary scan function pin description 20-pin tssop (vo20/vog20) vo20/vog20 top view ds123_02_071304 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 d0 (dnc) clk tdi tms tck cf oe/reset (dnc) ce vccj vcco vccint tdo (dnc) (dnc) ceo (dnc) gnd (dnc) platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 39 r xcfxxp pinouts and pin descriptions vxcfxxp o48/vog48 and fs48/fsg48 pin names and descriptions ta bl e 1 4 provides a list of the pin names and descriptions fo r the xcfxxp 48-pin vo48/vog48 and 48-pin fs48/fsg48 packages. ta bl e 1 4 : xcfxxp pin names and descripti ons (vo48/vog48 and fs48/fsg48) pin name boundary scan order boundary scan function pin description 48-pin tsop (vo48/ vog48) 48-pin tfbga (fs48/ fsg48) d0 28 data out d0 is the data output pin to provide data for configuring an fpga in serial mode. d0-d7 are the data output pins to provide parallel data for configuring a xilinx fpga in selectmap (parallel) mode. the d0 output is set to a high-impedance state during ispen (when not clamped). the d1-d7 outputs are set to a high-impedance state during ispen (when not clamped) and wh en serial mode is selected for configuration. the d1-d7 pins can be left unconnected when the prom is used in serial mode. 28 h6 27 output enable d1 26 data out 29 h5 25 output enable d2 24 data out 32 e5 23 output enable d3 22 data out 33 d5 21 output enable d4 20 data out 43 c5 19 output enable d5 18 data out 44 b5 17 output enable d6 16 data out 47 a5 15 output enable d7 14 data out 48 a6 13 output enable clk 01 data in configuration clock input. an internal programmable control bit selects between the internal oscillator and the clk input pin as the clock source to cont rol the configuration sequence. each rising edge on the clk input increments the internal address counter if the clk input is selected, ce is low, oe/reset is high, busy is low (parallel mode only), and cf is high. 12 b3 oe/reset 04 data in output enable/reset (open-drain i/o). when low, this input holds th e address counter reset and the data and clkout outputs are placed in a high-impedance state. this is a bidirectional open-drain pin that is held low while the prom completes the internal power-on reset sequence. polarity is not programmable. 11 a3 03 data out 02 output enable ce 00 data in chip enable input. when ce is high, the device is put into low-power standby mode, the address counter is reset, and the data and clkout outputs are placed in a high-impedance state. 13 b4 cf 11 data in configuration pulse (open-drain i/o). as an output, this pin allows the jtag config inst ruction to initiate fpga configuration without powering down the fpga. this is an open-drain signal that is pulsed low by the jtag config command. as an input, on the rising edge of cf , the current design revision selection is sampled and the internal address counter is reset to the start addr ess for the selected revision. if unused, the cf pin must be pulled high using an external 4.7 k pull-up to v cco . 6d1 10 data out 09 output enable platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 40 r ceo 06 data out chip enable output. chip enable output (ceo ) is connected to the ce input of the next prom in the chain. this output is low when ce is low and oe/reset input is high, and the internal address counter has been incremented beyond its terminal count (tc) value. ceo returns to high when oe/reset goes low or ce goes high. 10 d2 05 output enable en_ext_sel 31 data in enable external selection input. when this pin is low, design revision selection is controlled by the revision select pins. when this pin is high, design revision selection is controlled by the internal programmable revision select control bits. en_ext_sel has an internal 50k resistive pull-up to v cco to provide a logic 1 to the device if the pin is not driven. 25 h4 rev_sel0 30 data in revision select [1:0] inputs. when the en_ext_sel is low, the revision select pins are used to select the design revision to be enabled, overriding the internal programmable revision select cont rol bits. the revision select[1:0] inputs have an internal 50 k resistive pull-up to v cco to provide a logic 1 to the device if the pins are not driven. 26 g3 rev_sel1 29 data in 27 g4 busy 12 data in busy input. the busy input is enabled when parallel mode is selected for configuration. when busy is high, the internal address counter stops incrementing and the current data remains on the data pins. on the first rising edge of clk after busy transitions from high to low, the data for the next address is driven on the data pins. when serial mode or decompression is enabled during device programming, the busy input is disabled. busy has an internal 50 k resistive pull-down to gnd to provide a logic 0 to the device if the pin is not driven. 5c1 clkout 08 data out configuration clock output. an internal programmable control bit enables the clkout signal, which is sourced from either the internal oscillator or the clk input pin. each rising edge of the selected clock source increments the internal address counter if data is available, ce is low, and oe/reset is high. output data is available on the rising edge of clkout. clkout is disabled if ce is high or oe/reset is low. if decompression is enabled, clkout is parked high when decompressed data is not ready. when clkout is disabled, the clkout pin is put into a high-z state. if clkout is used, then it must be pulled high externally using a 4.7 k pull-up to v cco . 9c2 07 output enable tms mode select jtag mode select input. the state of tms on the rising edge of tck determines the state transitions at the test access port (tap) controller. tms has an internal 50 k resistive pull-up to v ccj to provide a logic 1 to the device if the pin is not driven. 21 e2 tck clock jtag clock input. this pin is the jtag test clock. it sequences the tap controller and all the jtag test and programming electronics. 20 h3 tdi data in jtag serial data input. this pin is the serial input to all jtag instruction and data registers. tdi has an internal 50 k resistive pull-up to v ccj to provide a logic 1 to the device if the pin is not driven. 19 g1 tdo data out jtag serial data output. this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50k resistive pull-up to v ccj to provide a logic 1 to the system if the pin is not driven. 22 e6 vccint +1.8v supply. positive 1.8v supply voltage for internal logic. 4, 15, 34 b1, e1, g6 ta bl e 1 4 : xcfxxp pin names and descripti ons (vo48/vog48 and fs48/fsg48) (continued) pin name boundary scan order boundary scan function pin description 48-pin tsop (vo48/ vog48) 48-pin tfbga (fs48/ fsg48) platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 41 r xcfxxp vo48/vog48 pinout diagram vcco +3.3v, 2.5v, or 1.8v i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the output voltage drivers and input buffers. 8, 30, 38, 45 b2, c6, d6, g5 vccj +3.3v or 2.5v jtag i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the tdo output voltage driver and tck, tms, and tdi input buffers. 24 h2 gnd ground 2, 7, 17, 23, 31, 36, 46 a1, a2, b6, f1, f5, f6, h1 dnc do not connect. (these pins must be left unconnected.) 1, 3, 14, 16, 18, 35, 37, 39, 40, 41, 42 a4, c3, c4, d3, d4, e3, e4, f2, f3, f4, g2 ta bl e 1 4 : xcfxxp pin names and descripti ons (vo48/vog48 and fs48/fsg48) (continued) pin name boundary scan order boundary scan function pin description 48-pin tsop (vo48/ vog48) 48-pin tfbga (fs48/ fsg48) figure 16: vo48/vog48 pinout diagram (top view) with pin names ds123_24_070505 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vo48/vog48 top view dnc gnd dnc vccint busy cf gnd vcco clkout ceo oe/reset clk ce dnc vccint dnc gnd dnc tdi tck tms tdo gnd d7 d6 gnd vcco d5 d4 dnc dnc dnc dnc vcco dnc gnd dnc vccint d3 d2 gnd vcco d1 d0 rev_sel1 rev_sel0 en_ext_sel vccj platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 42 r xcfxxp fs48/fsg48 pin names xcfxxp fs48/fsg48 pinout diagram ta bl e 1 5 : xcfxxp pin names (fs48/fsg48) pin number pin name pin number pin name a1 gnd e1 vccint a2 gnd e2 tms a3 oe/reset e3 dnc a4 dnc e4 dnc a5 d6 e5 d2 a6 d7 e6 tdo b1 vccint f1 gnd b2 vcco f2 dnc b3 clk f3 dnc b4 ce f4 dnc b5 d5 f5 gnd b6 gnd f6 gnd c1 busy g1 tdi c2 clkout g2 dnc c3 dnc g3 rev_sel0 c4 dnc g4 rev_sel1 c5 d4 g5 vcco c6 vcco g6 vccint d1 cf h1 gnd d2 ceo h2 vccj d3 dnc h3 tck d4 dnc h4 en_ext_sel d5 d3 h5 d1 d6 vcco h6 d0 figure 17: fs48/fsg48 pinout diagram (top view) 123456 ds121_01_071604 a b c d e f g h fs48/fsg48 top view platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 43 r ordering information valid ordering combinations marking information XCF01SVo20 c xcf08pvo48 c xcf08pfs48 c x cf01svog20 c xcf08pvog48 c xcf08pfsg48 c xcf02svo20 c xcf16pvo48 c xcf16pfs48 c x cf02svog20 c xcf16pvog48 c xcf16pfsg48 c xcf04svo20 c xcf32pvo48 c xcf32pfs48 c x cf04svog20 c xcf32pvog48 c xcf32pfsg48 c xcf04s vo20 c operating range/processing c = (t a = ?40 c to +85 c) package type vo20 = 20-pin tssop package vog20 = 20-pin tssop package, pb-free device number xcf01s xcf02s xcf04s xcf32p fs48 c operating range/processing c = (t a = ?40 c to +85 c) package type vo48 = 48-pin tsop package vog48 = 48-pin tsop package, pb-free fs48 = 48-pin tfbga package fsg48 = 48-pin tfbga package, pb-free device number xcf08p xcf16p xcf32p xcf04s -v operating range/processing c = (t a = ?40 c to +85 c) package type v = 20-pin tssop package (vo20) vg = 20-pin tssop package, pb-free (vog20) vo48 = 48-pin tsop package (vo48) vog48 = 48-pin tsop package, pb-free (vog48) f48 = 48-pin tfbga package (fs48) fg48 = 48-pin tfbga package, pb-free (fsg48) device number xcf01s xcf02s xcf04s xcf08p xcf16p xcf32p platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 44 r revision history the following table shows the revision history for this document. date version revision 04/29/03 1.0 xilinx initial release. 06/03/03 1.1 made edits to all pages. 11/05/03 2.0 major revision. 11/18/03 2.1 pinout corrections as follows: ? ta bl e 1 4 : ? for vo48 package, removed 38 from vccint and added it to vcco. ? for fs48 package, removed pin d6 from vccint and added it to vcco. ? ta bl e 1 5 (fs48 package): ? for pin d6, changed name from vccint to vcco. ? for pin a4, changed name from gnd to dnc. ? figure 16 (vo48 package): for pin 38, changed name from vccint to vcco. 12/15/03 2.2 ? added specification (4.7k ) for recommended pull-up resistor on oe/reset pin to section "reset and power-on reset activation," page 22 . ? added paragraph to section "standby mode," page 22 , concerning use of a pull-up resistor and/or buffer on the done pin. 05/07/04 2.3 ? section "features," page 1 : added package styles and 33 mhz configuration speed limit to itemized features. ? section "description," page 1 and following: added state conditions for cf and busy to the descriptive text. ? table 2, page 3 : updated virtex-ii configuration bitstream sizes. ? section "design revisioning," page 9 : rewritten. ? section "prom to fpga configuration mode and connections summary," page 10 and following, five instances: added instruction to tie cf high if it is not tied to the fpga?s prog_b (program ) input. ? figure 6, page 14 , through figure 13, page 21 : added footnote indicating the directionality of the cf pin in each configuration. ? section "i/o input voltage tolerance and power sequencing," page 22 : rewritten. ? table 12, page 23 : added cf column to truth table, and added an additional row to document the low state of cf . ? section "absolute maximum ratings," page 24 : revised v in and v ts for ?p? devices. ? section "supply voltage requirements for power-on reset and power-down," page 24 : ? revised footnote callout number on t oer from footnote (4) to footnote (3). ? added footnote (2) callout to t vcc . ? section "recommended operating conditions," page 25 : ? added typical (typ) parameter columns and parameters for v ccint and v cco /v ccj . ? added 1.5v operation parameter row to v il and v ih , ?p? devices. ? revised v ih min, 2.5v operation, from 2.0v to 1.7v. ? added parameter row t in and max parameters ? (continued on next page) 05/07/04 (cont?d) 2.3 (cont?d) ? section "dc characteristics over operating conditions," page 26 : ? added parameter row and parameters for paralle l configuration mode, ?p? devices, to i cco . ? added footnote (1) and footnote (2) with callouts in the test conditions column for i ccj , i ccints , i ccos , and i ccjs , to define active and standby mode requirements. ? section "ac characteristics over operating conditions," page 27 : ? corrected description for second t cac parameter line to show parameters for 1.8v v cco . ? revised footnote (7) to indicate v cco = 3.3v. ? applied footnote (7) to second t cyc parameter line. ? section "ac characteristics over operating conditions when cascading," page 36 : revised footnote (5)t cyc min and t cac min formulas. ? table 14, page 39 : ? added additional state conditions to clk description. ? added function of resetting the internal address counter to cf description. platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 45 r 07/20/04 2.4 ? added pb-free package options vog20, fsg48, and vog48. ? figure 6, page 14 , and figure 7, page 15 : corrected connection name for fpga dout (optional daisy-chained slave fpgas with diff erent configurations) from dout to din. ? section "absolute maximum ratings," page 24 : removed parameter t sol from table. (t sol information can be found in package user guide .) ? table 2, page 3 : removed reference to xc2vp125 fpga. 10/18/04 2.5 ? table 1, page 1 : broke out v cco / v ccj into two separate columns. ? table 9, page 7 : added clarification of id code die revision bits. ? table 10, page 8 : deleted t ckmin2 (bypass mode) and renamed t ckmin1 to t ckmin . ? ta bl e "recommended operating conditions," page 25 : separated v cco and v ccj parameters. ? ta bl e "dc characteristics over operating conditions," page 26 : ? added most parameter values for xcf08p, xcf16p, xcf32p devices. ? added footnote (1) to i cco specifying no-load conditions. ? ta bl e "ac characteristics over operating conditions," page 27 : ? added most parameter values for xcf08p, xcf16p, xcf32p devices. ? expanded footnote (1) to include xcf08p, xcf16p, xcf32p devices. ? added footnote (8) through (11) relating to clkout conditions for various parameters. ? added rows to t cyc specifying parameters for parallel mode. ? added rows specifying parameters with decompression for t clko , t coh , t ff , t sf . ? added t ddc (setup time with decompression). ? ta bl e "ac characteristics over operating conditions when cascading," page 36 : ? added most parameter values for xcf08p, xcf16p, xcf32p devices. ? separated footnote (5) into footnotes (5) and (6) to specify different derivations of t cyc , depending on whether dual-purpose configurat ion pins persist as configuration pins, or become general i/o pins after configuration. 03/14/05 2.6 ? added virtex-4 lx/fx/sx configuration data to ta bl e 2 . ? corrected virtex-ii configuration data in ta b l e 2 . ? corrected virtex-ii pro configuration data in ta b l e 2 . ? added spartan-3l configuration data to ta bl e 2 . ? added spartan-3e configuration data to ta b l e 2 . ? paragraph added to fpga master selectmap (parallel) mode (1) , page 11 . ? changes to dc characteristics ? t oer changed, page 26 . ? i ol changed for v ol , page 26 . ? v cco added to test conditions for i il , i ilp , i ihp ,and ii h , page 26 . values modified for i ilp and i ihp. ? changes to ac characteristics ? t lc and t hc modified for 1.8v, page 31 . ? new rows added for t cec and t oec , page 30 . ? minor changes to grammar and punctuation. ? added explanation of "preliminary" to dc and ac electrical characteristics. 07/11/05 2.7 ? move from "preliminary" to "product specification" ? corrections to virtex-4 configuration bitstream values ? minor changes to figure 7, page 15 , figure 12, page 20 , figure 13, page 21 , and figure 16, page 41 ? change to "internal oscillator," page 8 description ? change to "clkout," page 8 description platform flash in-system programmable configuration proms ds123 (v2.9) may 09, 2006 www.xilinx.com 46 r 12/29/05 2.8 ? update to the first paragraph of "ieee 1149.1 boundary-scan (jtag)," page 5 . ? added jtag cautionary note to page 5 . ? corrected logic values for erase/program (e r/prog) status field, ir[4], listed under "xcfxxp instruction register (16 bits wide)," page 6 . ? sections "xcfxxs and xcfxxp prom as configuration slave with clk input pin as clock source," page 27 , "xcfxxp prom as configuration ma ster with clk input pin as clock source," page 30 and "xcfxxp prom as configuration master with internal oscillator as clock source," page 33 added to "ac characteristics over operating conditions," page 27 . ? notes for figure 6, page 14 , figure 7, page 15 , figure 8, page 16 , figure 9, page 17 , figure 10, page 18 , figure 11, page 19 , figure 12, page 20 , and figure 13, page 21 updated to specify the need for a pull-up resistor if cf is not connected to progb. ? enhanced description under section "clkout," page 8 . ? enhanced description on design revision sampling under section "design revisioning," page 9 . ? figure 4 and figure 5 renamed to table 7, page 6 and table 8, page 6 respectively. all tables, figures, and table and figure references renumber this point forward. ? value for "iccint," page 26 updated from 5ma to 1ma for xcfxxp. ? block diagram in figure 2, page 2 updated to show clock source muxing and route clocking to all functional blocks. 05/09/06 2.9 ? added virtex-5 lx support to table 2, page 3 . ? "vil" maximum for 2.5v operation in "recommended operating conditions," page 25 updated to match lvcmos25 standard. |
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